Sires Labs, the designer of high speed optical microchips has introduced a version of their transceiver chip which consumes 50% less power than competitors using conventional methods. The new version of this optical PMD (transceiver) chip integrates the Transimpedance Amplifier, (TIA), Limiting Amplifier, VCSEL driver, Digital Diagnostics (Control & Status) and LVDS interface which are typically available as individual components. Hence the resultant saving in power and also board space. The product, as well as an Evaluation Board are available for sampling.
The transceiver chip is optimised for speeds ranging from 1 Gbps to 3.125Gbps and consumes just 210mW of power. This drop in power is brought about by the integration of many of the functions into the one chip. Using conventional methods all the functions could require as many as three chips with their respective power consumption. The conventional method results in decreased efficiency due to its higher consumption of power.
he SRL3101NST is designed for use with VCSELs and PIN/APDs in VSR applications such as Gigabit Ethernet, SONET VSR Links, Intra- system, Backplanes, SAN, Fibre Channel and Terabit Routers and Switches. This chip is competitively priced for its high performance and enables smaller form factors without compromising the signal quality. Because of the integration it also reduces manufacturing costs and component count in the development of VSR modules and systems. SiRES also offers the SRL3104TS which is a quad channel 12.5Gbps transmitter.
The integrated chips main features include, a single +3.3V operation, peak-to-peak jitter of 20ps (PRBS23); modulation and bias currents of up to 10mA each controllable via an external analogue voltage or digitally through the internal registers via a standard two wire serial interface; integrated temperature sensor; internal closed loop feedback for temperature compensation without the need for an external monitor photodiode; adjustable VCSEL diode monitor comparator window; tolerates photodiode input capacitances of up to 1 pF; input current range from 15uA to 800uA; a programmable threshold for low input signal detect feature and an average input current monitor output. The digital status signals are accessible via internal registers or through the serial digital interface.
The SRL3101NST is available as a bare die with large bond pad pitches. Using the CMOS Process, the chip has been designed using SiRES’ in house developed dynamic self adaptive biasing (dSAB) technology that compensates for process and temperature induced parametric variations and allows for a higher yield of analogue circuits in the CMOS process.
